1. Field of the Invention
Generally, the present invention relates to sophisticated integrated circuits, and, more particularly, to using in situ doping and substantially diffusionless annealing for forming embedded stressor regions to enhance the performance of semiconductor devices such as transistor elements and the like.
2. Description of the Related Art
In modern ultra-high density integrated circuits, device features have been steadily decreasing in size to enhance the performance of the semiconductor device and the overall functionality of the circuit. In addition to an increase in the speed of operation due to reduced signal propagation times, reduced feature sizes allow an increase in the number of functional elements in the circuit in order to extend its functionality. Today, advanced semiconductor devices may include features having a critical size of 32 nm or even less.
The fabrication of integrated circuits requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach, due to the superior characteristics in view of operating speed and/or power consumption. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel (NMOS) transistors and P-channel (PMOS) transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated from the channel by a thin gate insulating layer, or gate dielectric. In operation, an appropriate control voltage is applied to the gate electrode, which thereby forms a conductive channel below the gate electrode. The conductivity of the channel region depends on several factors, including dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Therefore, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the reduction of the channel length, and the commensurate reduction of the channel resistivity, renders the channel length a dominant design criteria for accomplishing an increase in the operating speed of the integrated circuits.
The continuous shrinkage of the transistor dimensions, however, carries with it a plurality of issues which have to be addressed so as to not unduly offset the advantages that may be obtained by steadily decreasing the channel length of MOS transistors, such as the development of enhanced photolithography and etch strategies necessary to reliably and reproducibly create circuit elements having very small critical dimensions for new device generations. Given the general processing difficulties associated with the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, other mechanisms have been utilized in an effort to increase charge carrier mobility in the channel region of transistor elements and thereby enhance overall device performance. For example, in one approach, the dopant concentration within the channel region may be reduced, thereby reducing scattering events for the charge carriers and thus increasing the conductivity. However, reducing the dopant concentration in the channel region significantly affects the threshold voltage of the transistor device, thereby making a reduction of the dopant concentration a less attractive approach unless other mechanisms are developed to adjust a desired threshold voltage. In another approach, the lattice structure in the channel region may be modified, for instance by creating tensile or compressive stress, which results in a modified mobility for electrons and holes. For example, creating a tensile stress in the channel region increases the mobility of electrons, wherein, depending on the magnitude of the tensile stress, an increase in mobility of up to 20% may be obtained, which, in turn, may directly translate into an increased channel conductivity and a corresponding improvement in NMOS transistor performance. On the other hand, a compressive stress in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of PMOS transistors.
One common approach for inducing a desired level of stress in the channel region of some semiconductor devices is through the use of stressed overlayers. In practice, a stressed overlayer—i.e., a material layer having an intrinsic internal stress—is formed above the transistor elements, and the intrinsic stress of the stressed overlayer is transferred through the gate electrode and any sidewall spacer elements to the channel region below the gate dielectric layer. The stressed overlayer method, however, has some inherent drawbacks. For example, once formed, the stressed overlayer must typically remain in place throughout all remaining process steps, so that the beneficial stresses imparted to the channel region by the stressed overlayer is maintained in the final device configuration. Furthermore, the presence of any intermediate device elements or material layers between a stressed overlayer and the targeted channel region of a MOS transistor—such as the aforementioned gate electrode, sidewall spacer elements and gate dielectric layer—may tend to mitigate the level of stress than can be transferred through those elements or layers to the channel. Additionally, since the type of intrinsic stress used to increase hole mobility along the channel length of PMOS transistor elements (i.e., a compressive stress) differs from the type of stress used to increase electron mobility along the channel length of NMOS transistor elements (i.e., a tensile stress), different materials and deposition parameters may be required to form each type of stressed overlayer. Moreover, sophisticated photolithography and/or etching techniques may also be necessary to facilitate the formation of stressed overlayers, thus increasing overall processing complexity and costs, while potentially reducing product yield.
One promising technique for inducing the desired state of stress in the channel region of PMOS transistors—which may be used in lieu of, or possibly even in combination with, the stressed overlayer approach described above—is to embed stressed material regions in the active area of the PMOS device. This approach involves forming cavities in the device substrate adjacent to the gate electrode structure of the PMOS device, and then epitaxially forming a stressed silicon-based semiconductor material, such as silicon-germanium, in the cavities. This epitaxially formed material tends to induce the desired compressive stress in the channel region of the PMOS device, as will be described more fully below.
FIGS. 1a-1f depict one illustrative prior art integration scheme that has been used for forming a CMOS device that includes both NMOS and PMOS transistors, wherein a stressed material region is formed in the active area adjacent to the channel region of the PMOS device. More specifically, FIG. 1a shows a simplified schematic cross-sectional view of an illustrative semiconductor device 100 during an early stage of manufacturing. The device 100 includes an illustrative substrate 101, which may represent any appropriate carrier material for having formed thereon or thereabove a semiconductor layer 103.
The device 100 may generally include device regions 100N and 100P in which illustrative NMOS and PMOS transistor elements 150n and 150p, respectively (see FIG. 1f), may be formed during later manufacturing stages, as will be discussed in further detail below. The device regions 100N and 100P may include active areas 105n and 105p, respectively, which may in turn be defined and enclosed by isolation structures 104, as illustrated in FIG. 1a. In certain illustrative embodiments, the isolation structures 104 may be provided in the form of a shallow trench isolation, as may typically be used for sophisticated integrated circuits. Additionally, the active areas 105n, 105p may also include an appropriate dopant species for establishing the requisite conductivity type. For example, a p-type dopant, such as boron or boron difluoride, may be incorporated into the active area 105n so as to form a p-well, in and above which may be formed NMOS transistor elements. On the other hand, an n-type dopant, such as phosphorous or arsenic and the like, may be incorporated into the active area 105p, thereby forming an n-well in and above which PMOS transistors may be formed.
In the manufacturing stage depicted in FIG. 1a, gate electrode structures 120n and 120p have been formed in the device regions 100N and 100P and above the active areas 105n and 105p, respectively. Each of the gate electrode structures 120n and 120p may include a plurality of layers and materials, depending on the desired transistor element types and overall integration scheme. For example, in some CMOS integrations, the transistor architecture may be based on a conventional gate insulating layer and polysilicon gate electrode (polySiON) configuration, wherein the materials making up each of the gate electrode structures 120n and 120p are adapted accordingly. On the other hand, transistor architecture for both gate electrode structures 120n and 120p may be based on a more advanced high-k dielectric and metal gate electrode (HK/MG) configuration, wherein a high-k dielectric material should be understood to be a material having a dielectric constant, or “k-value,” of approximately 10 or greater. Furthermore, in still other CMOS integrations, the respective gate electrode structures 120n and 120p may also have substantially different configurations from one another (e.g., polySiON vs. HK/MG, or vice versa), again depending on the overall device design criteria. However, for simplicity, the illustrative gate electrode structures 120n and 120p of FIG. 1a are both depicted as being based on a conventional polySiON gate electrode configuration, as will now be described.
As shown in FIG. 1a, each of the gate electrode structures 120n and 120p may be made up of, for example, a gate insulation layer 107, which may typically be a silicon dioxide or silicon oxynitride material layer, and a gate electrode 108 made of, for example, polysilicon material. Furthermore, the gate insulation layers 107 of the gate electrode structures 120n and 120p may separate the gate electrodes 108 from channel regions 106n and 106p, respectively, therebelow. Additionally, the gate electrode structures 120n, 120p may also include a gate cap layer 109 that is made up of, for example, silicon nitride, and which is adapted to protect the gate electrode 108 during subsequent device processing, such as during etch steps and the like. The gate electrode structures 120n, 120p shown in FIG. 1a may be formed using techniques that are well known to those skilled in the art, e.g., depositing and/or forming a stack of material layers as may be appropriate for the specific gate electrode type, followed by performing one or more etching processes to define the gate electrode structures 120n, 120p, including the gate cap layers 109 positioned thereabove.
FIG. 1b depicts the illustrative semiconductor device 100 of FIG. 1a after several manufacturing operations have been performed, some of which will now be described. First, a spacer layer 114, such as, for example, silicon nitride and the like, is blanket-deposited above the device 100, so as to cover both of the device regions 100N and 100P. Thereafter, an etch mask (not shown) is formed above the device 100 and patterned so that the etch mask covers the NMOS device region 100N and exposes at least a portion of the spacer layer formed above the PMOS device region 100P. A selective anisotropic etching process, such as a reactive ion etch (RIE) process and the like, is then performed so as to form sidewall spacers 114s on the sidewalls of the gate electrode structure 120p, and to remove the exposed portion of the spacer layer 114 from above the active area 105p. Next, one or more etching processes are performed to define a plurality of cavities 115 in the semiconductor material 103, i.e., in the active area 105p of the PMOS region 100P. During these one or more etching processes, the gate electrode 108 of the gate electrode structure 120p may be substantially protected from the effects of the etch chemistries by the sidewall spacers 114s and the gate cap layer 109. Furthermore, the remaining portions of the spacer layer 114 may act as a hard mask to protect the NMOS device region 100N and any covered portions of the PMOS device region 100P.
The position of the cavities 115 relative to a channel region 106p below the PMOS gate electrode structure 120p is typically determined by the thickness 114t of the sidewall spacers 114s, and will ultimately affect the level of stress that can be induced in the channel region 106p. Furthermore, the width 115w and depth 115d of the cavities 115 may vary depending on the particular device application and/or processing requirements. For example, in some applications, the depth 115d may range anywhere from 50-70 nm, and the width 115w may extend across the active area 105p from a point that is substantially aligned with and below the sidewall spacers 114s, and over to the trench isolation structures 104 that define the extent of the active area 105p. However, cavities 115 having a narrower width 115w may also be used, as is shown for the illustrative semiconductor device 100 of FIG. 1b. 
After the cavities 115 have been formed in the active area 105p, an epitaxial deposition process is then performed so as to form an embedded stressor material region 117 in the cavities 115. In one example, a two-step epitaxial process may be used to form the embedded stressor material region 117, in which case the region 117 may include a first material layer 117a that is an undoped layer of silicon-germanium (SiGe) material having a germanium content of approximately 20%, and which may tend to impart a compressive stress in the channel region 106p, as will be further discussed below. Furthermore, the embedded stressor material region 117 may also include a second material layer 117b that is made up of an undoped material layer that is substantially silicon. In certain applications, the use of the second material layer 117b that is substantially made up of silicon may be necessary so as to avoid material agglomeration problems that may potentially occur when, during later processing steps, a nickel silicide contact region is formed in a layer of material that includes some amount of germanium, resulting in a so-called “spotty” nickel silicide contact. The presence of an upper material layer in the embedded stressor material region 117 that is substantially silicon—such as the second material layer 117b—may substantially avoid such “spotty” nickel silicide occurrences.
Depending upon the particular application, the thickness of the first material layer 117a may range from 40-50 nm, and in some cases may substantially fill the cavities 115, depending on the device processing parameters and/or the degree of compressive stress required. Furthermore, when used, the second material layer 117b may have a thickness that ranges from 15-20 nm, which would typically correspond to the approximate thickness of any nickel silicide material formed in the contact regions of the active area 105p. Additionally, in some cases the complete embedded stressor material region 117 may have a raised upper surface 117s relative to an interface of the channel region 106p and the gate insulating layer 107.
As is well known to those having skill in the art, during an epitaxial deposition process, the material comprising the silicon-based substrate acts as a “seed crystal.” Therefore, during the epitaxial deposition process, silicon-based materials will only be formed on the exposed surfaces of silicon-containing semiconductor materials. On the other hand, surfaces that are covered by dielectric materials such as silicon nitride, silicon dioxide and the like, will be effectively “masked.” Therefore, as shown in FIG. 1b, epitaxially deposited material will not be formed on, for example, the spacer layer 114 present above the NMOS device region 100N and portions of the PMOS device region 100P. Furthermore, epitaxially deposited material will not be formed on the sidewall spacers 114s, or the gate cap layer 109 of the gate electrode structure 120p. 
While, in general, the silicon-based material comprising the semiconductor layer 103—e.g., the PMOS active area 105p—will act as a “seed layer” during epitaxial deposition, the epitaxially deposited embedded stressor material regions 117 may also take on a lattice structure and crystal orientation that is substantially identical to those of the semiconductor layer 103 in the active area 105p. Furthermore, due to the relatively larger covalent radius of germanium atoms as compared to silicon atoms, the lattice structure of an unrestrained SiGe semiconductor material is generally larger than that of an unrestrained semiconductor material that is substantially silicon. Accordingly, when a SiGe semiconductor material is epitaxially deposited on a substantially crystalline silicon material—such as, for example, the semiconductor layer 103—the restrained lattice structure of the SiGe material may induce a localized stress on the surrounding lattice structure of the substantially silicon material of the semiconductor layer 103. In this way, an epitaxially deposited semiconductor material region comprising SiGe that is formed in the cavities 115 of the active area 105p—such as the first material layer 117a of the embedded stressor material region 117—may induce a compressive stress (indicated by arrows 162) on the channel region 106p of the PMOS transistor elements formed in the device region 100P. Accordingly, an overall improvement in device performance may be realized due to an enhanced hole mobility, as previously described.
As shown in FIG. 1c, a selective etch process 130, which may include multiple etching steps, is thereafter performed to remove the remaining portions of the spacer layer 114 (i.e., the hardmask layer) from above the device regions 100N and 100P, the sidewall spacers 114s, and the cap layers gate 109 from the gate electrode structures 120n and 120p. Then, as shown in FIG. 1d, first spacer elements 124 are formed adjacent to the sidewall of the NMOS and PMOS gate electrode structures 120n and 120p, respectively, using material layer deposition and etching techniques well known in the art. At this point, one or more ion implantation sequences are performed so as to form certain doped regions in the active areas 105n, 105p, such as, for example, a tilt-angle implantation sequence 131 to form halo implant regions 141, and/or a shallow implantation sequence 132 to form extension implant regions 142, and the like. As should be appreciated by those of ordinary skill, the implantation sequences 131 and 132 may each include various masking and implantation steps, and the implantation parameters, such as implantation energy, ion/dopant type, implant angle, and the like, may vary according to the specific transistor type and device design criteria. Furthermore, it should be appreciated that the thickness of the first spacer elements 124 is typically adjusted as required to establish the position and extent of the device extension and/or halo implant regions 142, 141.
As shown in FIG. 1e, second spacer elements 125 are then formed adjacent to the first spacer elements 124 based on techniques and materials known in the art, as noted previously. Thereafter, a deep ion implantation sequence 133 is performed so as to form deep source and drain regions 143 in the active areas 105n, 105p of the PMOS and NMOS device regions 100N, 100P, based on masking and implantation techniques, dopant materials, and the like, that are known to those skilled in the art. As with the first spacer elements 124 above, the thickness of the second spacer elements 125 may also be adjusted so as to properly locate the deep source and drain implant regions 143 relative to the gate electrode structures 120n, 120p and the channel regions 106n, 106p. 
As shown in FIG. 1f, the illustrative semiconductor device 100 may then be subjected to a heat treating process 134 that is adapted to: 1) repair any damage that may have occurred to the crystalline lattice structure of the active areas 105n and 105p during the ion implantation sequences 131, 132 and/or 133; and 2) activate any implanted dopant materials.
In one example of a typical state-of-the-art process flow, the heat treating process 134 may include a rapid thermal annealing (RTA) process, sometimes referred to as a spike annealing process. Typically, an RTA anneal is performed in the range of 1000-1100° C., where the temperature is above the 1000° C. level for approximately 10 seconds, and a peak temperature of around 1100° C. is maintained for approximately 2 seconds. In certain cases, the RTA process may be supplemented by a second annealing process so as to maximize dopant activation. For example, an ultra-fast annealing (UFA) process of extremely short duration, such as, for example, a flash lamp annealing process, a laser spike annealing (LSA) process, and the like, may be performed after the RTA anneal. Generally, the UFA anneal is performed at a higher temperature than the RTA anneal, but for a significantly shorter amount of time, such as, for example, a total time that is up to 3-4 orders of magnitude shorter in duration. For example, in a typical UFA process, a peak temperature in the range of 1200-1300° C. may be achieved, but the process may only last for approximately 10 milliseconds, or even less.
As a result of the dopant activation that occurs during the heat treating process 134, source and drain regions 144 of the NMOS and PMOS transistor elements 150n, 150p, respectively (schematically depicted in FIG. 10 may be established and corresponding P-N junctions created in the active areas 105n and 105p of the device regions 100N and 100P, respectively. Additional processing operations may then be performed to complete fabrication of the semiconductor device 100; e.g., forming metal silicide regions on the source/drain regions 144 and/or the gate electrodes 108, forming various contact elements and metallization layers, etc.
One problem associated with the prior art process flow described above is that the epitaxially formed embedded stressor material regions 117 are subjected to various implantation sequences as described above—e.g., a halo region implantation sequence 131, an extension region implantation sequence 132, and a source/drain implantation sequence 133. During one or more of the implantation sequences, the embedded stressor material regions 117 may suffer associated damage to the lattice structure of one or both of the first and second material layers 117a, 117b, which may sometimes cause at least a partial stress relaxation of the embedded stressor material regions. Additionally, when the semiconductor device 100 is subjected to the heating process 134 so as to repair any such lattice structure damage and to activate the implanted dopant ions, the embedded stressor material regions 117 may sometimes have a tendency to relax, particularly the constrained SiGe material of the first material layer 117a. As a result, the embedded stressor material regions 117 may ultimately impart a lesser degree of compressive stress 162 in the channel region 106p of the PMOS transistors 150p. This in turn may tend to reduce the performance capabilities of the PMOS transistor elements 150p formed in the device region 100P, as well as that of any semiconductor device 100 that may include such PMOS transistors 150p. Moreover, the above-described process flow does not incorporate any steps that would tend to impart a tensile stress in the active area 105n of the device region 100N, which might otherwise positively affect the mobility of electrons in the channel region 106n of the NMOS transistors 150n and enhance the performance capabilities thereof.
Furthermore, it should be appreciated that during the typical heat treating process performed to heal any crystalline damage and to activate implanted dopants, such as the heat treating process 134 described above, the dopant atoms will commonly diffuse to one degree or another through the semiconductor material of the active areas 105n, 105p. Such dopant diffusion is schematically depicted by the change between the as-implanted extension and deep source/drain regions 142 and 143 shown in FIG. 1e, and the final as-annealed source/drain regions 144 as shown in FIG. 1f. For some semiconductor devices, the amount of dopant diffusion may be planned and optimized as part of the overall device integration scheme, so as to define and set the location of the P-N junctions of the respective devices. However, as semiconductor devices are aggressively scaled from the 32 nm design node down to the 28 nm or 22 nm nodes, or even smaller, critical dimensions such as gate length and the like are significantly decreased. In such aggressively scaled devices, even small amounts of unwanted dopant diffusion in critical device areas—such as the channel regions 106n and/or 106p of the transistors 150n and/or 150p—may be undesirable, as it could cause detrimental short channel behavior in some devices, thereby leading to a commensurate overall decrease in device performance.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.